This invention relates to a PLL (Phase Locked Loop) circuit and an optical communication reception apparatus, and more particularly to a PLL circuit which includes a phase detection circuit and a frequency detection circuit and an optical communication reception apparatus which uses a PLL circuit as a production circuit for a clock signal to be used for retiming processing of receive data.
FIG. 11 shows a configuration of a PLL circuit which is used commonly. Referring to FIG. 11, the PLL circuit shown includes a phase detection (PD) circuit 101 and a frequency detection (FD) circuit 102 and operates in the following manner.
First, the frequency detection circuit 102 performs phase comparison between an input signal DATA and clock signals (ICLK, QCLK). Then, the frequency of a frequency clock VCOCLK of a voltage-controlled oscillator (VCO) 106 is controlled through a charge pump (CP) circuit 104 and a loop filter 105 based on a result of the comparison to pull the oscillation frequency of the VCO 106 to a target oscillation frequency. The clock signals (ICLK, QCLK) are produced based on the oscillation frequency clock VCOCLK of the VCO 106 by a clock generator 107.
Then, the phase detection circuit 101 performs phase comparison between the input signal DATA and the oscillation frequency clock VCOCLK of the VCO 106. Then, the phase detection circuit 101 controls the phase of the oscillation frequency clock VCOCLK of the VCO 106 through another charge pump circuit 103 and the loop filter 105 based on a result of the comparison to cause the phase of the frequency clock VCOCLK of the VCO 106 to align with the phase of the input signal DATA.
In a PLL circuit of the type described, a frequency comparison circuit of such a configuration as shown in FIG. 12 is conventionally used for the frequency detection circuit 102. In the following, a detailed circuit configuration and operation of the frequency detection circuit 102 are described.
It is assumed here that the digital signal DATA inputted to the frequency detection circuit 102 has a non-return-to-zero (NRZ) waveform. It is also assumed that the clock generator 107 divides the oscillation frequency clock VCOCLK of the VCO 106 to a predetermined dividing ratio 1/n (in the example described, n=1) to produce the clock signal ICLK and shifts the phase of the clock signal ICLK by 90 degrees to produce the clock signal QCLK, and the clock signals ICLK and QCLK are inputted to the frequency detection circuit 102.
First, a data input terminal 111 to which the input signal DATA of an NRZ waveform is inputted is connected to the D (data) input terminal of a D-type flip-flop (D-FF) 112 and connected also to an input terminal A of an exclusive OR (EX-OR) gate 113. Meanwhile, an ICLK input terminal 114 to which the clock signal ICLK is inputted is connected to an input terminal A of each of a pair of AND gates 116 and 117 while a QCLK input terminal 115 to which the clock signal QCLK is inputted is connected to the other input terminals B of the AND gates 116 and 117. The input terminal A of the AND gate 117 is a negated input terminal through which the clock signal ICLK is inputted with the reversed polarity.
The output terminals of the AND gates 116 and 117 are connected to the D input terminals of D-FFs 118 and 119, respectively. The output terminal of the EX-OR gate 113 is connected to the CLK input terminals of the D-FFs 118 and 119. The Q output terminals of the D-FFs 118 and 119 are connected to the D input terminals of D-FFs 120 and 121, and the Q output terminals of the D-FFs 120 and 121 are connected to the D input terminals of D-FFs 122 and 123, respectively. The CLK terminals of the D-FF 112 and the D-FFs 120 to 123 are connected to the ICLK input terminal 114.
The Q output terminal of the D-FF 122 is connected to an input terminal A of an AND gate 124. The Q output terminal of the D-FF 123 is connected to an input terminal B of another AND gate 125. The Q output terminal of the D-FF 120 is further connected to an input terminal A of the AND gate 125, and the Q output terminal of the D-FF 121 is connected to an input terminal B of the AND gate 124. The output terminals of the AND gates 124 and 125 are connected to circuit output terminals 126 and 127, respectively.
A DOWN pulse signal for controlling the VCO 106 of FIG. 11 to lower the oscillation frequency of it is extracted as an output signal from the AND gate 124 while an UP pulse signal for controlling the VCO 106 to raise the oscillation frequency is extracted as an output signal from the AND gate 125 The DOWN pulse signal and the UP pulse signal are supplied to the charge pump circuit 104 of FIG. 11 through the circuit output terminals 126 and 127, respectively.
Now, circuit operation of the frequency detection circuit having the configuration described above is described with reference to a timing chart of FIG. 13. In FIG. 13, waveforms (a) to (o) indicate waveforms at nodes (a) to (o) of FIG. 12, respectively.
First, the clock signal ICLK (a) has a pulse waveform wherein it rises to the “H” (high) level at time t0 and falls to the “L” (low) level at time t2. Similarly, the clock signal ICLK (a) rises at times t4, t8, t12, . . . and falls at times t6, t10, . . . . The clock signal ICLK (a) is supplied to the input terminals A of the AND gates 116 and 117 through the ICLK input terminal 114 and supplied also to the CLK terminals of the D-FF 112 and the D-FFs 120 to 123.
The clock signal QCLK (b) has a pulse waveform having a phase shifted by 90 degrees, more particularly, delayed by 90 degrees with respect to the clock signal ICLK (a). In particular, the clock signal QCLK (b) rises to the “H” level at times t1, t5, t9, . . . and falls to the “L” level at times t3, t7, t11, . . . . The clock signal QCLK (b) is supplied to the input terminals B of the AND gates 116 and 117.
The AND gate 116 logically ANDs the clock signal ICLK (a) and the clock signal QCLK (b). Therefore, the output signal (c) of the AND gate 116 exhibits the “H” level within those periods within which both of the clock signals ICLK and QCLK have the “H” level, that is, within the period from time t1 to time t2, the period from time t5 to time t6 and the period from time t9 to time t10. Within the other periods, that is, within the period from time t0 to time t1, the period from time t2 to time t5, the period from time t6 to time t9 and the period from time t10 to time t12, the output signal (c) of the AND gate 116 exhibits the “L” level.
Meanwhile, the AND gate 117 logically ANDs the inverted clock signal ICLKX of the clock signal ICLK (a) and the clock signal QCLK (b). Therefore, the output signal (d) of the AND gate 117 exhibits the “H” level within those periods within which both of the clock signals ICLKX and QCLK have the “H” level, that is, within the period from time t2 to time t3, the period from time t6 to time t7 and the period from time t10 to time t11. Within the other periods, that is, within the period from time t0 to time t2, the period from time t3 to time t6, the period from time t7 to time t10 and the period later than time t11, the output signal (d) of the AND gate 117 exhibits the “L” level.
In the timing chart of FIG. 13, the period within which the output signal (c) exhibits the “H” level is represented as a period A while the period within which the output signal (d) exhibits the “H” level is represented as a period B.
Meanwhile, the NRZ input signal DATA (f) is supplied immediately to the input terminal A of the EX-OR gate 113 through the data input terminal 111 and supplied also to the D input terminal of the D-FF 112. The D-FF 112 fetches the “H” level/“L” level of the input waveform to the D input terminal at the timing of a rising edge of the clock signal ICLK (a). In this instance, if the input signal DATA (f) has the “H” level at time t0, then since the D-FF 112 fetches this, the level of the Q output signal (e) thereof changes to the “H” level.
Then, since the input signal DATA (f) changes between times t1 and t2 and reverses its polarity, the D-FF 112 fetches the input signal DATA (f) of the “L” level and changes its Q output signal (e) to the “L” level at the timing of a next rising edge of the clock signal ICLK (a). Further, since the polarity of the input signal DATA (f) reverses again between times t6 and t7, the D-FF 112 fetches the input signal DATA (f) of the “H” level at the next rising timing t8 of the clock signal ICLK (a) and changes its Q output signal (e) to the “H” level. Thereafter, the D-FF 112 keeps the “H” level until time t12.
The Q output signal (e) of the D-FF 112 is supplied to the input terminal B of the EX-OR gate 113. The EX-OR gate 113 exclusively ORs the Q output signal (e) supplied to the input terminal B and the input signal DATA (f) supplied to the input terminal A. As a result, as can be seen from the timing chart of FIG. 13, the level of the output signal (g) of the EX-OR gate 113 changes from the “L” level to the “H” level when the input signal DATA (f) reverses during the period from time t1 to time t2, and changes back to the “L” level at time t4 at which the Q output signal (e) of the D-FF 112 exhibits a level change to the “L” level.
For the period after time t4 until a next data reversal of the input signal DATA (f), the output signal (g) of the EX-OR gate 113 maintains the “L” level. Then, when the input signal DATA (f) reverses within the period from time t6 to time t7, the output signal (g) of the EX-OR gate 113 exhibits a level change from the “L” level to the “H” level at the timing of the reversal.
Thereafter, at time t8, the level of the Q output signal (e) of the D-FF 112 changes from the “L” level to the “H” level. Consequently, the EX-OR gate 113 logically ORs the “H” level of the input signal DATA (f) and the “H” level of the Q output signal (e), and therefore, the level of the output signal (g) of the EX-OR gate 113 changes to the “L” level. Then, within the following period from time t8 to time t12, the level of the output signal (g) of the EX-OR gate 113 does not exhibit a change.
The output signals (c) and (d) of the AND gates 116 and 117 are inputted to the D input terminals of the D-FFs 118 and 119 in the next stage, respectively. The D-FFs 118 and 119 receive the output signal (g) of the EX-OR gate 113 as inputs to the CLK terminals thereof, and fetch the D input waveforms at the timing of a rising edge of the clock waveform and output the fetched levels as the Q output signals (h) and (k), respectively.
Since the output signal (g) of the EX-OR gate 113 rises within the period from time t1 to time t2 and, within the period, the output signal (c) of the AND gate 116 has the “H”, level and the output signal (d) of the AND gate 117 has the “L” level, the Q output signal (h) of the D-FF 118 exhibits the “H” level and the Q output signal (k) of the D-FF 119 exhibits the “L” level.
The timing at which the level of the output signal (g) of the EX-OR gate 113 changes from the “L” level to the “H” level is a changing point of the input signal DATA (f) within the period from time t6 to time t7. Since the output signal (c) of the AND gate 116 has the “L” level and the output signal (d) of the AND gate 117 has the “H” level at the timing, the level of the Q output signal (h) of the D-FF 118 changes from the “H” level to the “L” level and the level of the Q output signal (k) of the D-FF 119 changes from the “L” level to the “H” level. Thereafter, the levels are maintained until time t12.
The Q output signals (h) and (k) of the D-FFs 118 and 119 are supplied to the D input terminals of the D-FFs 120 and 121, respectively. The D-FFs 120 and 121 receive the clock signal ICLK (a) as the CLK inputs thereto and fetch the D input waveforms at the timing of a rising edge of the waveform of the clock signal ICLK (a). Here, the timing of the rising edge of the clock signal ICLK (a) is time t4, and since the Q output signal (h) of the D-FF 118 has the “H” level and the Q output signal (k) of the D-FF 119 has the “L” level at the timing, the level of the Q output signal (i) of the D-FF 120 becomes the “H” level and the level of the Q output signal (1) of the D-FF 121 becomes the “L” level.
The next rising edge timing of the clock signal ICLK (a) is time t8 and the Q output signal (h) of the D-FF 118 has the “L” level then. Therefore, the level of the Q output signal (i) of the D-FF 120 changes to the “L” level. Meanwhile, since the level of the Q output signal (k) of the D-FF 119 is the “H” level, the level of the Q output signal (1) of the D-FF 121 changes to the “H” level. The levels of the Q output signals (i) and (l) are maintained until time t12.
The Q output signals (i) and (l) of the D-FFs 120 and 121 are inputted to the D input terminals of the D-FFs 122 and 123 in the next stage, respectively. Also the D-FFs 122 and 123 receive the clock signal ICLK (a) as the CLK inputs thereto and fetch the D input waveforms at the timing of a rising edge of the waveform. Here, the rising edge timing of the clock signal ICLK (a) is time t8 and the D-FFs 122 and 123 fetch the levels of the Q output signals (i) and (l) of the D-FFs 120 and 121, respectively. Consequently, the level of the Q output signal (j) of the D-FF 122 changes to the “H” level and the level of the Q output signal (m) of the D-FF 123 changes to the “L” level.
The timing at which the clock signal ICLK (a) rises subsequently is time t12, and the Q output signal (i) of the D-FF 120 has the “L” level and the Q output signal (l) of the D-FF 121 has the “H” level at the timing. Therefore, the level of the Q output signal (j) of the D-FF 122 changes from the “H” level to the “L” level while the level of the Q output signal (m) of the D-FF 123 changes from the “L” level to the “H” level.
The Q output signal (j) of the D-FF 122 is supplied to the input terminal A of the AND gate 124. The Q output signal (l) of the D-FF 121 is supplied to the input terminal B of the AND gate 124. Consequently, the level of the DOWN pulse signal which is the output signal (n) of the AND gate 124 changes to the “L” level because the Q output signal (l) of the D-FF 121 changes to the “L” level at time t4. Then, at time t8, since both of the levels of the Q output signals (l) and (j) of the D-FFs 121 and 122 change to the “H” level, the level of the DOWN pulse signal changes to the “H” level.
Then at time t12, since the level of the Q output signal (l) of the D-FF 121 does not change and remains at the “H” level, the level of the Q output signal (j) of the D-FF 122 changes from the “H” level to the “L” level. Consequently, the level of the output signal (n) of the AND gate 124, that is, the level of the DOWN pulse signal, changes from the “H” level to the “L” level.
Meanwhile, the Q output signal (m) of the D-FF 123 is supplied to the input terminal B of the AND gate 125. The Q output signal (i) of the D-FF 120 is supplied to the input terminal A of the AND gate 125. Consequently, the UP pulse signal which is the output signal (o) of the AND gate 125 exhibits the “L” level because the levels of the Q output signals (i) and (m) of the D-FFs 120 and 123 change to the “L” level at time t8. Then at time t12, the level of the Q output signal (m) of the D-FF 123 changes to the “H” level. However, since the level of the Q output signal (i) of the D-FF 120 remains at the “L” level, the output signal (o) of the AND gate 125 maintains the “L” level.
From the foregoing, the frequency detection circuit of FIG. 12 generally operates in the following manner. If (ICLK, QCLK)=(0, 1) are sampled at a certain DATA changing point of time and then (ICLK, QCLK)=(1, 1) are sampled at the next DATA changing point of time, then an UP pulse signal of a duration equal to one period of the clock signal ICLK is outputted. In particular, if data of m bits (m is an arbitrary integer) is present between the two DATA changing points of time, then since this signifies that less than m cycles of the clock signal ICLK are present within the period, in order to raise the frequency of the clock signal ICLK, a pulse or pulses of the UP pulse signal are produced.
On the other hand, if (ICLK, QCLK)=(0, 1) are sampled at a certain DATA changing point of time and then (ICLK, QCLK)=(0, 0) are sampled at the next DATA changing point of time, then a DOWN pulse signal of a duration equal to one period of the clock signal ICLK is generated. Thus, if data of m′ bits (m′ is an arbitrary integer) is present between the two DATA changing points of time, since this signifies that more than m′ cycles of the clock signal ICLK are present within the period, in order to lower the frequency of the clock signal ICLK, a pulse or pulses of the DOWN pulse signal are produced.
When the frequencies of the clock signal ICLK and the input signal DATA fully coincide with each other, one of (0, 0), (0, 1), (1, 0) and (1, 1) is successively sampled at each DATA changing point of time, and neither the UP pulse signal nor the DOWN pulse signal is generated.
In this manner, the output signal (n) of the AND gate 124 is supplied as the DOWN pulse signal and the output signal (o) of the AND gate 125 is supplied as the UP pulse signal to the charge pump circuit 104 shown in FIG. 11. Then, the DOWN/UP pulse signal is used to control the charge pump circuit 104 to smooth (rectify) the output current of the charge pump circuit 104 to generate a control voltage for the VCO 106 through the loop filter 105.
The operation of the frequency detection circuit 102 in the foregoing description relates to operation when the duty ratios of the input signal DATA and the clock signals (ICLK and QCLK) are 100% and 50%, respectively. However, particularly in optical communication or the like, the transmission signal DATA suffers from some duty distortion as seen from the waveform (b) or (c) of FIG. 14, potentially giving rise to malfunction of the PLL circuit. FIG. 15 illustrates waveforms of the clock signals ICLK and QCLK and the transmission signal DATA when they suffer from some duty distortion.
As described hereinabove, in the conventional frequency detection circuit, the values of the clock signal ICLK and the clock signal QCLK are sampled at a changing point of time of the input signal DATA. Therefore, if the frequencies of the signals coincide fully with one each other, then the sample value within the period from time t2 to time t3 in FIG. 13 is “0” for the clock signal ICLK and “1” for the clock signal QCLK; the sample value within the period from the next DATA changing point t6 to time t7 is “0” for the clock signal ICLK and “0” for the clock signal QCLK; and if a DATA changing point is present within the period from time t10 to time t11, then the sample value at the point of time is “0” for the clock signal ICLK and “1” for the clock signal QCLK. Thus, it can be seen that the sample values at the three changing points are equal to one another.
However, as can be seen from the timing chart of FIG. 15, which illustrates a timing relationship when the input signal DATA is distorted and has a different duty ratio, whereas the clock signal QCLK is obtained by delaying the phase of the clock signal ICLK by 90 degrees, if the duty ratio of the input signal DATA increases and the width for one bit of the “H” level thereof becomes greater than the period of the clock signal ICLK, then if the input signal DATA rises within the period from time t1 to time t2, then the level of the clock signal ICLK is “1” and the level of the clock signal QCLK is “1” at the rising edge of the input signal DATA.
Then, when the input signal DATA exhibits a falling edge within the period from time t7 to time t8, both of the levels of the clock signal ICLK and the clock signal QCLK exhibit “0”, and the sample values of the clock signals ICLK and QCLK at the rising edge and the falling edge of the input signal DATA exhibit a variation from (1, 1) to (0, 0). Consequently, the frequency detection circuit malfunctions apparently.
On the other hand, if the duty ratio of the input signal DATA decreases and the width of one bit of the “H” level thereof becomes smaller than the period of the clock signal ICLK, then both of the levels of the clock signals ICLK and QCLK exhibit “0” at a rising edge of the input signal DATA within the period from time t3 to time t4. However, both of the levels of the clock signals ICLK and QCLK exhibit “1” at a falling edge of the input signal DATA within the period from time t5 to time t6. Consequently, the sample values of the clock signals ICLK and QCLK exhibit a change from (0, 0) to (1, 1).
As a result, the frequency detection circuit malfunctions. In other words, since in the conventional frequency detection circuit the clock signal ICLK and the clock signal QCLK are sampled at both rising and falling changing points of the input signal DATA, that is, in a 1/2 period of the input signal DATA, if the input signal DATA is distorted and the duty ratio varies, then the circuit malfunctions.